1. Field of the Invention
The present invention relates generally to semiconductor burn-in systems and more specifically it relates to a semiconductor burn-in thermal management system for providing an effective thermal management system capable of maintaining a desirable junction temperature spread amongst a batch of semiconductors being burned-in simultaneously.
2. Description of the Related Art
Thermal management systems for semiconductor burn-in equipment have been in use for years. Conventional thermal management systems utilized today are comprised of, for example, either air-cooled enclosures, or fluid-cooled cold plates. Upcoming technologies include refrigeration systems or other two-phase based technologies.
When producing semiconductors, manufacturers typically perform three different tests on the semiconductors prior to shipping: (1) sort, (2) burn-in, and (3) class testing. Sort test requires maintaining the wafers at a modest temperature, e.g. 35° Celsius, while the wafers are probed for defects. Conventional fluid-cooled cold plates are employed at this stage. Projected heat fluxes, even at the wafer sort, are pointing to the fact that a more effective thermal management technology is needed at this stage.
Burn-in of the semiconductors is typically accomplished utilizing elevated voltages and temperatures in a process that raises the junction temperatures of a batch of semiconductors. The lifespan of a semiconductor is closely related to its operating temperature wherein operating under increased temperatures reduces the effective lifespan of the semiconductor. By applying increased voltages and temperatures to a semiconductor, the weaker semiconductors will fail during testing. The length of the burn-in of semiconductors is directly tied to the median junction temperature of the batch of semiconductors. It is therefore important to maintain a relatively narrow junction temperature spread that provides a higher median temperature. For example, a poor thermal management system can produce a junction temperature spread from 75° to 125° Celsius resulting in a low median junction temperature, longer burn-in time and higher associated burn-in costs. Modern fluid-based thermal management systems are currently able to lower the junction temperature spread to approximately 95° to 110° Celsius thereby reducing burn-in time and burn-in costs.
Class test is the final step in the testing process and is comprised of a final series of tests to validate functionality and quantify speeds. During class test, non-uniform heating of the semiconductors typically occurs. A semiconductor's speed is typically derated by 0.15% for every degree Celsius rise above the target temperature (junction temperature, Tj). It is therefore important to maintain the temperature of the semiconductors relatively close to the target temperature (Tj).
Due to increasing chip heat fluxes (projected to exceed 125 W/cm2 by the year 2004), conventional thermal management systems for semiconductor burn-in are reaching their cooling limits. A further problem with conventional thermal management systems is that they are inefficient, complex, costly to implement and costly to operate. A further problem with conventional thermal management systems is that the resulting junction temperature spreads result in relatively long burn-in times of the semiconductor devices. Another problem with conventional thermal management systems is that they require significant amounts of power to operate.
Examples of patented devices which may be related to the present invention include U.S. Pat. No. 5,579,826 to Hamilton et al.; U.S. Pat. No. 5,582,235 to Hamilton et al.; U.S. Pat. No. 5,515,910 to Hamilton et al.; U.S. Pat. No. 5,359,285 to Hashinaga et al.; U.S. Pat. No. 6,389,225 to Malinoski et al.; U.S. Pat. No. 6,114,868 to Nevill; U.S. Pat. No. 5,461,328 to Devereaux et al.; U.S. Pat. No. 6,181,143 to Ghoshal; U.S. Pat. No. 6,288,371 to Hamilton et al.; U.S. Pat. No. 5,532,610 to Tsujide et al.; U.S. Pat. No. 6,307,388 to Friedrich et al.; U.S. Pat. No. 6,175,498 to Conroy et al.; U.S. Pat. No. 6,359,456 to Hembree et al.; U.S. Pat. No. 5,541,524 to Tuckerman et al.; U.S. Pat. No. 5,220,804 to Tilton et al.; U.S. Pat. No. 6,016,969 to Tilton et al.; U.S. Pat. No. 6,108,201 to Tilton et al.; U.S. Pat. No. 6,104,610 to Tilton et al.; U.S. Pat. No. 5,933,700 to Tilton; U.S. Pat. No. 5,880,931 to Tilton et al.; U.S. Pat. No. 5,933,700 to Tilton; U.S. Pat. No. 5,713,327 to Tilton et al.; U.S. Pat. No. 5,860,602 to Tilton et al.; U.S. Pat. No. 5,314,529 to Tilton et al.; U.S. Pat. No. 6,205,799 to Patel et al.; U.S. Pat. No. 6,349,554 to Patel et al.; U.S. Pat. No. 5,380,956 to Loo et al.; U.S. Pat. No. 6,115,251 to Patel et al.; U.S. Pat. No. 6,421,240 to Patel; and U.S. Pat. No. 6,317,326 to Vogel et al. Examples of patent applications filed for devices which may be related to the present invention include U.S. Patent Application 2001/0002541 filed by Patel et al.; U.S. Patent Application 2002/0050144 filed by Patel et al.; and U.S. Patent Application 2001/0050164 filed by Wagner et al.
While these devices may be suitable for the particular purpose to which they address, they are not as suitable for providing an effective thermal management system capable of maintaining a desired semiconductor temperature during a burn-in cycle. Conventional semiconductor burn-in thermal management systems are inaccurate and inefficient thereby increasing the testing costs for a semiconductor manufacturer.
In these respects, the semiconductor burn-in thermal management system according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of providing an effective thermal management system capable of maintaining a desired semiconductor temperature during a burn-in cycle.